AN EFFICIENT PROGRAMMABLE FREQUENCY DIVIDER: COMPARISON TABLE

The table 1 shows the comparison of efficient PD and conventional PD. Conventional PD has two counter and consumes 38mW power and maximum dividing factor obtained 34.Efficient PD consumes only 24 mW and uses only one counter and maximum dividing factor obtained is 34.

Fig. 10 : Added ClkGenerator For Data-Dependant Pre-Charge Suppression
Fig10An Efficient Programmable Frequenc-10

CONCLUSIONS

A low-power PD based on a shared UC with a small control circuit, is presented in this paper. The use of RMCS generator enabled the adaptation of only one counter instead of using two counters in conventional divider. A glitch less DFF is also proposed for more power savings. Experimental results show that the proposed PD consumes around 12mW less power than conventional dividers. The PD proposed in this paper can provide the low-power for multi-standard frequency synthesizers Economy