Here a new architecture of a low power programmable divider for multi-standard frequency synthesizer, using reset and modulus control signal (RMS) generator. This divider involves only one counter, so that fanout of DMP is reduced and the duplicated counter operation is reduced as compared to conventional PD.

*A. Architecture of efficient PD*

The block diagram of proposed programmable divider consists of DMP, Up-counter (UC), Multiplexer (MUX), RMS generator in Fig 2.The DMP divides the input signal Fin by either N or N+1 depending on modulus control (MC) signal value, and generates Dout. In this project DMP is designed for N=4 and then modified for N=16 for getting higher dividing factor. It will perform divide-by-4 (Div-4) when MC is high and divide-by-5 (Div-17) when MC is low. The Up Counter (UC) which increase the counter output (Cout) on the rising edge of Dout and reset Cout asynchronously when reset (RST) is high.

The ‘MUX’ select signal which value is equal to MC . When MC signal is low MUX output Mout should be ‘S’ which means UC counts the rising edge of Dout until S value. If both the count value(Cout) and S values become equal, RMS generator changes MC value from low to high. After the toggle DMP changes divide ratio from Div-5 to Div-4 and MUX select P value. Economy

*Fig. 2 : Block Diagram Of Efficient PD*

*Fig. 3 : Block Diagram of Improved PD*

Then, UC counts the rising edge of Dout until P value, if Dout and P values become equal, RMS generator changes MC value from high to low and generates high reset (RST) signal which resets Cout to zero. Thus, UC again counts rising edge of Dout from zero. As the processes described above repeated, the Efficient PD gives divide-by-D value.

D=SX (N+1) + (P-S) x N=N x p + S (2)

*B. Design of Reduced Module Control Signal Generator (RMCS)*

The RMCS generator consisting of an Equality detector, State machine in Fig.3.The equality detector generates a high equality signal (Eout) when the counting value (CNT) reaches the external control value, S and P. The state machine generates two control signals, MC and RST, for PD operations. Therefore the proposed PD adopts only a shared counter instead of the two counters used in the conventional programmable divider.

The operation of the RMCS generator when S = 2 and P = 6. DFF1 toggles at every rising edge of Eout and it changes the state of MC that mean Eout goes high every counter value became 2 and 6. At the first rising edge of Eout, the division ratio changes from Div-5 to Div-4, and at the second rising edge, the division ratio changes reversely from Div-4 to Div-5. DFF2 latches Vdd when the MC is changed from high (Div-4) to low (Div-5) and it generates a high RST signal to reset DFF1, DFF2.

*Fig. 5 : Equality detector for 3bit inputs *

*DESIGN OF DUAL MODULUS PRESCALAR FOR N=4*

The DMP block operates at the high speed in the frequency synthesizer and a large portion of the power is consumed in the PD. Fig. 4.4 shows the block diagram of the DMP, which consists of three DFFs and two logic gates. The MC signal is used to select the Div-4 or Div-5 function. In the Div-4 operation as shown in Fig. 5b, the input of the DFF3, which goes to D3, is always low. Thus, the DFF3 does not toggle.

*Fig. 6 : Block Diagram Of DMP DESIGN OF DMP FOR N=16*

The DMP block operates at the highest speed in the frequency synthesizer and consumes a large portion of the power in the PD. In Fig.6 shows the block diagram of the modified DMP (16/17) prescaler typically consists of a divide-by-4/5 synchronous core, a divide-by-4 asynchronous divider and a feedback logic section. The 4/5 MC signal controls how many DFFs the prescaler input signal must travel through and therefore determines the division ratio. When the 4/5 MC is held low, the core always divides the input signal by 4 which then travels through asynchronous divide-by-4 circuit, resulting in a total division ratio of 16. If the 4/5 MC signal is high, the core will divide by 5. If feedback is produced such that the core is modulated to divide-by-5 once and by 4 three times the resulting division ratio is 17.

A. Design of True Single Phase Clock (TSPC) FF. The TSPC DFF is generally known to consume less power than the common source logic (CSL) DFF because of there being no static DC currents.

*Fig. 8 : Schematic Diagram of TSPC DFF*

When the DMP is implemented using a conventional TSPC DFF .The internal node B of the DFF is pre-charged and discharged with clock transitions, therefore the unnecessary toggling generates glitches on its internal stage when the input D value keeps low. In other words, when D keeps low and clk runs continuously then node A stays high which makes the M1 set to ‘on’ state. Then, the middle-stage gate functions as an inverter and generates glitches on node B, which dissipate unwanted power consumption.

*B. Design of Glitch less D-FF*

The proposed glitch less DFF is given in the figure 9 and added clk generator for data-dependent pre-charge is shown in the figure 10. When input D stays low, the clk signal remains high and removes the charge-and-discharge operation at node B. This additional circuit occupies a small area and consumes only a negligible portion of DFF power since the switching activities of the D and A nodes are very low when compared to that of clk.

Although, the capacitive load on the clock path increases because of the added clk generator, since the proposed DMP uses only one glitch less DFF as DFF3.

**Table 1**