Frequency synthesizer is one of the major building blocks in modern communication synthesizers, which are widely used to implement various standards such as global systems for mobile communication, personal communications services, wideband code division multiple access, global positioning systems .In conventional phase-locked loop (PLL) based integer frequency synthesizer it generates a multiplied output frequency (Fout) from the reference frequency (Fref), where the frequency Fout is controlled by the division ratio D. So a programmable frequency divider (PD) is an essential block in the high speed integrated circuit. The PD takes a dominant portion of the power consumption in the frequency synthesizer, reducing the PD power is becoming one of the fundamental design considerations .A dual modulus prescaler (DMP), which is the front-end of the PD, divides the high-frequency clock generated from the VCO. Since the DMP is operating at the highest frequency, it is the most power-hungry block in the PD.
Moreover, the two redundant counters, namely programmable counter (PC) and swallow counter (SC) shown in Fig.1 increase the output load capacitance of the DMP, thus increasing the overall PD power consumption. In this paper the proposed programmable divider is designed and a Conventional Programmable Divider (PD) with two counters are used to compare with the efficient programmable divider. In the proposed PD the redundant operations of the two counters are effectively removed using single counter and a small control circuit. A glitch less DFF is also used to remove the glitches effectively from the DFF in the Dual modulus prescaler (DMP). Financial Management
The rest of the paper is organized as follows: Section II describes the conventional programmable divider. Section III describes efficient programmable divider and section IV describes the design of DMP.