The conventional PD consists of DMP and Two counters a) Programmable counter (PC) b) Swallow counter (SC).The Dual Module Prescaler (DMP) divides the input signal (Fin) by either ‘N’ or ‘N + 1’ depending on the modulus control (MC) signal. Here DMP designed for N=4, which means that divide-by-5 (Div-5) and divide-by-4 (Div-4) operations are performed when the MC is low and high. The output from DMP is taken as Dout. The Swallow counter (SC) counts the rising edge of Dout up to the external input value S. When the SC counting value reaches S, modulus control (MC) is changed from low to high. Likewise, the PC counts the rising edge of Dout up to P and when the counter value reaches P, a reset pulse (RST) is generated from PC and both counters, SC and PC are reset. The divider can give a programmable division ratio ‘D’. Financial Management

D=S x (N +1) + (P-S) x N =N x P + S (1)

Where N is given by DMP design P is fed to the PC and S is fed to the SC. Here P and S are designed for three bit value. P is generally greater than S. In the PD operation mode, since the DMP drives both the PC and SC, the output load capacitance of the DMP is large and the power dissipation becomes large as well. Moreover, both the PC and SC keep counting the rising edge of Dout until the counting number reaches P and S, respectively,

Fig1An Efficient Programmable Frequenc-1
Fig. 1 : Conventional PD

where the simultaneous two counter operations leads to considerable power consumption.

A. Conventional PD simulation results

For obtaining a divisionfactor D=26, P value selected as 6 and S=2 (P>S). Here Dual Modulus Prescalar is designed for initial division ratio (N=4).Consider at the initial state the module control value (mc) is low and DMP divide the input signal by-5.So the output of DMP( Dout) contain single frequency pulse for five input pulse,Dout is feed to two counter Programmable counter(PC) and Swallow counter(SC) .For swallow counter( SC ) when the Dout value become equal to the external ‘S’ value, the swallow counter(SC) change the MC value from zero to one.At the same time DMP will perform Div-by-4 operation.The PC already finished two count and it continues to count till the count value equal to 6.When the PC counts reaches 6 (P=6 ) a reset signal is generated from PC . Both PC and SC reset and the circuit give single frequency for 26 pulses that means a divider by factor(D) of 26.

B. Disadvantage

Since DMP has to drive two counters in parallel in the conventional architecture, these two counters operate simultaneously at its maximum operating frequency. This may result in redundant power consumption and area. Fanout required for the DMP is also high. Counter operation required more power consumption so here two counters are working parallel.